library verilog;
use verilog.vl_types.all;
entity zl_2346_pre2 is
    port(
        clr             : in     vl_logic;
        clk             : in     vl_logic;
        set             : in     vl_logic;
        datain          : in     vl_logic_vector(15 downto 0);
        en              : out    vl_logic_vector(3 downto 0);
        codeout         : out    vl_logic_vector(7 downto 0)
    );
end zl_2346_pre2;
